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VLSI interview question and answers, VLSI interview Question with Answers, VLSI Interview Questions

  VLSI interview question and answers, VLSI interview Question with Answers, VLSI Interview Questions
 
Hi, Today i would like to share some more VLSI interview Question and answers.
vlsi, vlsi interview questions, Vlsi interview questions and answers
 
 
1. What do you mean by metastability?
When setup or hold window is violated in the flip flop then signal attains a unpredictable value or state which is  known as metastability.
2. What is  an MTBF? What it signifies?
  • MTBF- stand for Mean Time Before Failure
  • IT signifies Average time to next failure
3. How chance of the  metastable state failure can be reduced?
     The chance of Metastable state failure can be Reduced By
  • Lowering clock frequency
  • Lowering data speed
  • Using faster flip flop
4. What are  advantages of using synchronous reset ?
  • No metastability problem with the  synchronous reset (provided recovery and removal time for reset is taken care).
  • Simulation of  the  synchronous reset is easy.
5. Give  the disadvantages of using synchronous reset ?
  •  The  Synchronous reset is slow.
  • Implementation of synchronous reset requires more number of gates compared to the  asynchronous reset design.
  • An active clock is essential for the  synchronous reset design. Hence you can expect more power consumption.
6. What are the advantages of using the  asynchronous reset ?
  • Implementation of asynchronous reset requires less number of gates compared to the  synchronous reset design.
  •  The  Asynchronous reset is fast.
  • Clocking scheme is not necessary for an asynchronous design. Hence the  design consumes less power. Asynchronous design style is also one of latest design options to achieve low power. Design community is scrathing their head over asynchronous design possibilities.
7. What are the disadvantages of using the  asynchronous reset ?
  • Metastability problems are the  main concerns of asynchronous reset scheme (design).
  •  The Static timing analysis and DFT becomes difficult due to asynchronous reset.
8. What are the 3 fundamental operating conditions that determine  delay characteristics of gate? How operating conditions affect gate delay? 
  • Process
  • Voltage
  • Temperature
9. Is verilog/VHDL is  concurrent or sequential language?
  •  The Verilog and VHDL both are concurrent languages.
  • Any hardware descriptive language is concurrent in nature.
10. In a system with insufficient hold time, will slowing down  clock frequency help?
  • No.
  • Making data path slower can help hold time but it may result in  the  setup violation.
11. In a system with the  insufficient setup time, will slowing down the clock frequency help?
  • Yes.
Making data path faster can also help in  setup time but it may result in hold violation.

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